1. Field of the Invention
The present invention concerns a method of manufacturing a semiconductor device and the semiconductor device. More specifically, it relates to a method of manufacturing a semiconductor device for supplying a current in a vertical direction, and the semiconductor device.
2. Description of Related Art
Generally, in a semiconductor device controlling a large current, for example, insulated gate bipolar transistors (IGBT), metal-oxide semiconductor filed-effect transistor (MOSFET), diodes, or suchlike, an electronic circuit is formed on one surface of a silicon substrate, and a back surface electrode comprising a plurality of layers is formed at the back surface thereof.
FIG. 8 is an enlarged cross sectional view for a main portion of a semiconductor device 100 of a vertical IGBT structure disclosed in Japanese Patent No. 3,339,552. In the semiconductor device 100, an insulated gate bipolar transistor as an electronic circuit is formed over a silicon substrate. The semiconductor device 100 includes a P type emitter layer 101, an N type base layer 102, a P type base layer 103, an N type emitter layer 104, a gate oxide film 105, a gate electrode 106, an interlayer dielectric film 107, a surface electrode (Al electrode) 108, a back surface electrode 110. The back surface electrode 110 includes an Al layer 111, a Ti layer 112, an Ni layer 113, and an Au layer 114 stacked in this order from the side of the P type emitter layer 101.
The semiconductor device 100 is manufactured by way of the following steps. At first, an N type silicon wafer at a lower impurity concentration is provided, and an insulated gate structure is formed on the surface of the silicon wafer which is used as the N type base layer 102. A P type emitter layer 101 is formed on the back surface of the silicon wafer. Then, the back surface electrode 110 is formed over the P type emitter layer 101. Specifically, after forming the P type emitter layer, the silicon wafer back surface is cleaned to remove a spontaneous oxide film. Then, Al, Ti, Ni, and Au are deposited by using an apparatus capable of depositing them continuously (wafer temperature during vapor deposition: 260° C.). After depositing the films, a heat treatment is conducted at 400 to 450° C. to form an aluminum-silicon alloy layer at the boundary relative to the Al layer 111. Thus, an ohmic contact is attained between the silicon substrate and the back surface electrode 110.
FIG. 9A is an enlarged cross sectional view for a main portion of an IGBT type semiconductor device and FIG. 9B is a view for explaining the constitution of a back surface electrode 229, which is a fragmentary enlarged cross sectional view of a region A in FIG. 9A disclosed in Japanese Unexamined Patent Publication No. 2005-303218. A semiconductor device 200 has an N type silicon substrate 201 at a lower impurity concentration, a silicon oxide film 202, a field dielectric film 204, a P− type semiconductor layer 205, an N− type semiconductor region 206, a trench 207, a thermal oxide film 208, a gate electrode 209, a polycrystal silicon pattern 210, a dielectric film 211, an interconnection 217, a polyimide film 219, an N+ type semiconductor region 223, a P+ type semiconductor region 224, a back surface electrode 229. The back surface electrode 229 includes an Ni layer 225, a Ti layer 226, an Ni layer 227, and an Au layer 228 stacked in this order from the side of the silicon substrate 201.
The semiconductor device 200 is manufactured by way of the following steps. At first, a silicon wafer comprising N− type single crystal silicon is provided and an insulated gate structure is formed on the surface of the silicon wafer. The N+ type semiconductor region 223 is formed on the back surface of the silicon wafer by way of steps of implanting impurity ions having an N conduction type. Further, the P+ type semiconductor region 224 is formed in a region shallower than that by way of steps of implanting impurity ions having a P conduction type.
As the back surface electrode 229, after at first cleaning the silicon substrate 201 with hydrofluoric acid, Ni, Ti, Ni, and Au are deposited successively over the back surface of the semiconductor substrate 201 by a sputtering method or a vacuum vapor deposition method. After depositing the films, an alloying treatment (heating treatment) is conducted thereby reacting the Ni layer 225 and the P+ type semiconductor region (single crystal silicon) 224 to form a compound as an ohmic contact.
FIG. 10 is an enlarged cross sectional view for a main portion of a semiconductor device 300 of a P channel type power MOSFET structure disclosed in Japanese Unexamined Patent Publication No. 2007-19458. The semiconductor device 300 includes, as shown in FIG. 10, a P+ type silicon substrate 301, a P− type drift layer 302, an N type base region 303, an N type body layer 303a, an N+ type contact region 303b, a P+ type source region 304, a trench 305, a gate dielectric film 306, a gate electrode 307, an interlayer dielectric film 308, a surface electrode (source electrode) 309, a back surface electrode 310, a re-crystallized silicon layer 312. The back surface electrode 310 has an Al layer 310a, a Ti layer 310b, an Ni layer 310c, and an Au-layer 310d stacked in this order from the side of the silicon substrate.
The semiconductor device 300 is manufactured by way of the following steps. At first, a P+ type silicon wafer is provided and a gate trench structure is formed on the surface of the silicon wafer. Then, the back surface of the silicon wafer is polished. Thus, an amorphous silicon layer of 10 to 15 nm thickness (not illustrated) is formed. Then, the Al layer 310a is formed over the amorphous silicon layer by sputtering without wet etching the back surface of the P type silicon wafer. The energy in this step is set to 3 kW or higher. Thus, silicon atoms in the amorphous silicon layer are re-arranged together with aluminum atoms to form a recrystallized silicon layer 312 and an ohmic contact between the silicon substrate 301 and the back surface electrode 310 is obtained.